1. Field of the Invention
The present invention relates to a multi-bit test circuit for carrying out tests on a plurality of memory cells at the same time, and more specifically, to a multi-bit test circuit for determining a match or a mismatch in logical level among the data bits read out in parallel from the plurality of memory cells.
2. Description of the Background Art
One of the tests applied to a semiconductor memory device is a checking of seeing if data can be written to and read from memory cells correctly. In this checking, test data having a predetermined bit pattern are written in memory cells, then read therefrom, and then it is determined whether the read out data are matched with expected value data. When the readout data match the expected data, the semiconductor memory device is considered to operate properly, and on the other hand, when they mismatch each other, the semiconductor memory device is considered to contain a bit defect.
It would take too much time to execute this checking test on a semiconductor memory device with a large storage capacity on a bit by bit basis. In order to reduce the testing time, the test is executed in units of plural bits by utilizing a multi-bit test method. In the multi-bit test, multi-bit memory cells are selected concurrently, and test data bits of the same logical level are written to these memory cells. Then, stored data are read concurrently from these memory cells for determination of a match or a mismatch in logical level among the readout data bits.
In this multi-bit test, multi-bit memory cells are generally tested at the same time, which can reduce the test time as compared with the case where the readout data bits are checked on matching with the expected value data on a bit by bit basis. When the bit width is 256 bits as in an embedded DRAM (dynamic random access memory) and is larger than a standard DRAM, compression of the internal readout data of such large data bit width makes it possible to perform the test at higher speed with the use of a testing apparatus for the standard DRAM.
FIG. 8 shows an example of the structure of a conventional multi-bit test circuit. In this structure, 32-bit data D<0>-D<31> read out in parallel from a memory circuit MK are compressed to generate a 1-bit flag FLAG finally. The flag FLAG indicates a match or a mismatch in logical level among 32-bit data D<31:0>.
In FIG. 8, the multi-bit test circuit includes a buffer circuit BF for amplifying a specific data bit D<31>; EXOR circuits EX0-EX30 arranged corresponding to data bits D<30:0>, respectively, for receiving the data bits at their respective first inputs and also receiving the output signal of buffer circuit BF at their second inputs; and an OR circuit GT for receiving the output signals of EXOR circuits EX0-EX30 to generate the flag FLAG.
Each of EXOR circuits EX0-EX30 operates as a mismatch detection circuit and outputs a high level signal when the signals received to the first and second inputs thereof are different in logical level from each other. In the multi-bit test circuit shown in FIG. 8, a data bit D<31> is used as a teacher data, and it is determined whether the logical levels of each of data bits D<30:0> and the teacher data match or mismatch each other. When specific data bit D<30:0> is equal in logical level to all of data bits D<30>-D<0>, EXOR circuits EX0-EX30 all output low level signals, which makes flag FLAG from OR circuit GT go low. This low level of the flag FLAG indicates that all the memory cell data read out in parallel are equal in logical level, and it is determined that data writing and reading are properly performed in memory circuit MK.
When at least one of readout data bits D<30:0> is different in logical level from data bit D<31>, at least one of EXOR circuits EX0-EX30 outputs a high level signal, which makes flag FLAG from OR circuit GT go high. This high level of the FLAG indicates a mismatch in logical level among the memory cell data, thereby detecting the presence of a bit failure.
In this multi-bit test, before the memory cell data are read out, data of the same logical level are written in the corresponding memory cells in memory circuit MK. Therefore, in the structure shown in FIG. 8, it is possible to determine whether proper data writing and reading are done to the 32-bit memory cells concurrently, which greatly reduces the test time as compared with the case where the test is done bit by bit.
In the multi-bit test circuit shown in FIG. 8, specific memory cell data (data bit D<31>) read out inside is used as a teacher data, and it is determined whether data bits D<30:0> are properly read out or not. The use of specific data bit D<31> as the teacher data causes the gate load and interconnection line load of the teacher data to be large. Thus, buffer circuit BF is used to transfer data bit D<31> to EXOR circuits EX30-EX0 arranged corresponding to data bits D<30:0>. In order to transfer data bit D<31> commonly to EXOR circuits EX30-EX0, buffer circuit BF must have a comparatively large driving capability, thereby requiring a large chip area. This causes a problem that a large chip area is needed for the multi-bit test circuit.
The output signal line of buffer circuit BF is connected to all of EXOR circuits EX30-EX0, with a long interconnection length and a large interconnection line load. This interconnection of the teacher data causes another problem that the propagation delay of the output signal of buffer circuit BF may delay the defining timing, to make it unable to drive flag FLAG to the definite state condition quickly. In order to avoid this problem, buffer circuit BF must have a larger driving power, causing further problem of occupying even larger chip area.